In manufacturing semiconductors, it is required to form a fine wiring pattern along with a trend toward miniaturization of semiconductor devices. For example, Japanese Patent Application Publication No. 2001-507081 discloses a technique related to inductively coupled plasma CVD capable of forming a dielectric film having etching resistance. Japanese Patent Application Publication No. H10-284487 discloses a technique related to a method for depositing a dielectric Si—O—F film on a substrate. In addition, a technique for performing selective pattern formation while suppressing complication of processing is disclosed in Japanese Patent Application No. 2016-121820, and a technique for forming a film by filling SiN which is related to a technique for suppressing generation of deposits on a side surface is disclosed in Japanese Patent Application No. 2016-121826.
In the case of forming a fine wiring pattern, there is known, e.g., a technique for suppressing a film forming rate on a side surface by adding an etchant in an air gap process for a low-k film. In that case, a sufficient difference in an etching rate between layers may be required to maintain a pattern shape through a plurality of etching processes. However, in the case of forming layers having different etching rates along a predefined fine wiring pattern, complicated processes may be required. Therefore, there is required a technique of, while maintaining a shape of a pattern, easily laminating a layer having a shape corresponding to the pattern shape on the pattern.